Conventionally, if a data receiving apparatus needs data from a data transmitting apparatus, the data receiving apparatus always transmits a command signal firstly and then the data transmitting apparatus transmits data to the data receiving apparatus responding to the command signal. The operations for the data receiving apparatus and the data transmitting apparatus need to be synchronized, or the data maybe wrongly transmitted or wrongly sampled.
FIG. 1 is a block diagram illustrating a data transceiving system, which applies a common clock scheme, for related art. As shown in FIG. 1, the data transceiving system 100 comprises a data receiving apparatus 101 and a data transmitting apparatus 103. The data receiving apparatus 101 receives a common clock signal CCLK from the clock source 105 via a clock pin CP_1 and the data transmitting apparatus 103 receives the common clock signal CCLK from the clock source 105 via the clock pin CP_2. By this way, the data transmitting apparatus 103 outputs the data DA from the data pin DP_2 to the data pin DP_1 based on the common clock signal CCLK, and the data receiving apparatus 101 samples the data DA based on the common clock signal CCLK. That is, the data receiving apparatus 101 and a data transmitting apparatus 103 share the common clock signal CCLK to process the data DA.
However, the common clock signal CCLK received by the data receiving apparatus 101 and the data transmitting apparatus 103 may have phase skew due to the latency caused by transmitting path. Such issue becomes more serious if the data transceiving system operates at a high speed. Furthermore, if the data transmitting apparatus 103 is an I/O (input/output) apparatus, such scheme will limit the bandwidth of the data transmitting apparatus 103.
FIG. 2 is a block diagram illustrating a data transceiving system 200, which applies a source clock scheme, for related art. As illustrated in FIG. 2, the data receiving apparatus 201 and the data transmitting apparatus 203 for the data transceiving system 200 do not share a common clock signal to process data. The data receiving apparatus 201 transmits a master clock signal MCLK from a clock pin CP_11 thereof to a clock pin CP_21 of the data transmitting apparatus 203. The master clock signal MCLK is applied to operations other than processing the data DA. For example, the data receiving apparatus 201 outputs a command signal CMD from a command pin CMP_1 thereof to a command pin CMP_2 of the data transmitting apparatus 203 based on the master clock signal MCLK.
The data transmitting apparatus 203 outputs a data sampling clock signal SCLK from a clock pin CP_22 thereof to a clock pin CP_12 of the data receiving apparatus 201. The data transmitting apparatus 203 outputs data DA from a data pin DP_2 thereof to a data pin DP_1 of the data receiving apparatus 201 based on the data sampling clock signal SCLK, and the data receiving apparatus 201 samples data DA based on the data sampling clock signal SCLK. However, either the data receiving apparatus 201 or the data transmitting apparatus 203 needs an extra clock pin (i.e. clock pins CP_12, CP_22) for such scheme.